A Hierarchical Bridging Fault Extraction Approach for Vlsi Circuit Layouts

Bridging fault extraction and analysis are crucial to deriving high quality bridging fault test generation. As state-of-the-art designs integrate millions of logic gates into a VLSI circuit, a run-time and memory eecient bridging fault extraction approach must be developed to cope with the design complexity. In this paper, a hierarchical bridging fault analyzer-FAULTAN is described. In FAULTAN, the design hierarchy is followed while performing fault extraction resulting in both computation time and memory savings compared to the traditional at approach. As part of the hierarchical extraction strategy, a cell fault library is built a priori to help accelerate the bridging fault extraction process. Through the fully hierarchical extraction techniques, FAULTAN achieves on the average 5 times speedup and 1/10 memory usage as compared with an existing at fault extractor. The superior accuracy of FAULTAN is also demonstrated in this paper.